Neural system engineering has been attracting significant attention in recent years. Inspired by a biological brain with excellent flexibility and power efficiency, neural systems can be employed in many applications such as pattern recognition, machine learning and motor control. One of the biggest challenges of a practical neural system implementation is a hardware density. Neurons and synapses are the two fundamental components of a neural system whose quantity can be as high as billions. As an example, a human brain has approximately 1011 neurons, and the number of synapses is 103 to 104 times larger.
As a result, in order to implement practical neural systems, the synapse hardware is required to be extremely area and power eff. In recent years, a memristor element has been studied for implementation of a synapse because its cross-bar architecture can offer a very dense hardware solution. A single memristor with pulse width modulation (PWM) scheme was proposed in the prior art for implementation of the synapse with Spike-Timing-Dependent Plasticity (STDP) function. In order to have a reward-driving learning neural system, the synapse weight may need to be controlled by both the STDP mechanism and a dopamine signal. However, with the dopamine signal controlling, the synapse implementation may become very complex and not area/power efficient.